1. Field of the Invention
This invention pertains to a method for generating test patterns for use with a scan circuit so as to obtain an input series of test patterns for distinguishing a state without a failure from a state with a failure, including a degenerative failure.
Test pattern generation is a process of generating test patterns for use in an inspection process for distinguishing a defective part from a good part, which is indispensable for improving the reliability of an electronic circuit.
A circuit built on a printed circuit board can be used for detecting a failure such as a degenerative failure by directly observing a connection point in the circuit as well as inputting test patterns. However, it is impossible to directly observe a connecting point in a circuit structured as a semiconductor IC. Therefore, a large number of test patterns and a large amount of time has been required for inspecting a semiconductor integrated circuit.
An art is sought for reducing the test time during which test patterns are applied.
2. Description of the Related Arts
In general, a failure as an object for a test pattern generation is a degenerative failure of a signal line. This is a failure such that the logical value of a signal line in a circuit is fixed to either zero [0] or one [1].
FIGS. 1A and 1B are explanatory views of a sequential circuit, and FIG. 1C is an explanatory view of a scan circuit model.
FIG. 1A shows a generic synchronous sequential circuit, comprising a combinational circuit module 14 and a memory element unit 15, or memory element part, for storing the current state. A commonplace approach for use as a method for generating a test pattern for such a sequential circuit is to apply a combinational circuit method for generating a test pattern after repetitive expansions of the combinational circuit are preformed in a time direction.
The method is explained in the following literatures.
Kubo, H.: "A Procedure for Generating Test Sequences to Detect Sequential Circuit Failures", "NEC J. Res. Dev. (12), pp. 69-78, 1968".
Piteously, G. and Roth, J.: "A Heuristic Algorithm for the Testing of Asynchronous Circuits", IEEE Trans. Computers, Vol. C-20, No. 6, pp. 639-647, 1971.
A generic method for generating a test pattern such as this has problems that the processing can take an extremely large amount of time and that the failure detection rate by an obtained pattern is not always sufficient.
FIGS. 1B and 1C show an approach for making a method for generating test patterns for use in a combinational circuit be applicable especially to a large scale circuit through a conversion of a synchronous sequential circuit (shown in FIG. 1B) into a scan circuit (shown in FIG. 1C). As shown in FIG. 1C, a scan circuit is a circuit whose internal memory elements D, D, . . . are realized by shift registers such that all the memory elements can receive (write-in/scan-in) respective values from an external terminal and supply (read-out/scan-out) respective values to an external terminal. The internal memory elements are called scan registers.
The memory element unit 15 can switch between a parallel-in/parallel-out mode and a serial-in/serial-out mode by a mode switch input. When a plurality of registers receive a test pattern, the memory element unit 15 switches to the serial-in/serial-out mode, thereby serially receiving a test pattern in synchronization with a scan clock. Then, the memory element unit 15 switches to the parallel-in/parallel-out mode, and the combinational circuit unit 14 receives test pattern data via an output terminal SI. This enables the combinational circuit unit 14 to receive a test pattern. An external input terminal PI receives a test pattern on the external input side corresponding to the test pattern stored in the memory element unit 15.
The test pattern received by the combinational circuit unit 14 as a result of the above operations is outputted from the combinational circuit unit 14 after the test pattern is processed in the combinational circuit. A part of the result is outputted at an external output terminal PO and the rest is inputted to the memory element unit 15. Although the part of the result outputted from an external output terminal PO can be confirmed directly, the rest of the result inputted to the memory element unit 15 cannot be confirmed directly. To confirm the rest of the result, the memory element unit 15 switches at this time to a serial-in/serial-out mode, and by applying a scan clock, the result is read as serial data and confirms whether or not it is correct.
The memory element unit 15 minimizes the number of external pins by combining all memory elements in a form of a shift register.
Ordinarily, only four [4] pins, i.e. a scan-in terminal for supplying data, a scan-out terminal for reading data, one [1] type of clock terminal for driving a shift register, and one [1] type of mode switch terminal, are added.
A scan circuit in which all the memory elements are changed to scan registers is called a total scan circuit and a scan circuit in which a part of the memory elements are changed to scan registers is called a partial scan memory. The total scan circuit, for example, will be explained hereinafter.
Because a total scan circuit, in which all the memory elements are changed to scan registers, is capable of being read out and written in via an external terminal, when a test pattern is generated, an input to and an output from the memory element unit 15 shown in FIG. 1A are considered respectively as external outputs and external inputs. An application of a method for generating a test pattern to the combinational circuit unit 14 enables all non-redundant degenerative failures to be detected.
When a test pattern obtained in this manner is applied to an actual circuit comprising the sequential circuit which includes a combinational circuit and memory elements; of the obtained pattern, the part corresponding to the memory element unit 15 is written in (scanned-in) to a scan input terminal. After the external input value is set, a clock for operating the circuit is activated, and the value of the external output and the value read out (scanned-out) from the scan output terminal are observed.
FIG. 2 is a flowchart for explaining a conventional test procedure.
More specifically, FIG. 2 shows the procedure of a scan circuit for performing a test of a sequential circuit by using a test pattern generated by a conventional method for generating a test pattern as steps ST1 through ST6.
Step ST1
Determine whether any test pattern remains by attempting to extract a test pattern. When all test patterns have been examined, i.e. if no test pattern remains (NO), terminal the test (END). If a pattern remains (YES), invoke step ST2.
Step ST2
Set a test pattern in the memory element unit 15 by supplying the part corresponding to the memory element unit 15 from the scan input terminal. Continue to step ST3.
Step ST3
Set the rest of the test pattern as external input values. Continue to step ST4.
Step ST4 Activate the clock for driving the circuit.
Step ST5
Observe an external output value and a value read from the scan output terminal. Then, loop back to step ST1 and repeat similar processes for the next test pattern. A failure will be detected according to the observation values.
A total scan circuit has the following two [2] problems.
(1) An enlarged circuit size
(2) A prolonged test period
Generally, when a circuit has its internal memory elements replaced with a shift register, the circuit size increases by about twenty percent [20%] and the circuit's operating speed deteriorates slightly. To avoid these problems, a partial scan circuit may be used in which only some but not all memory elements are replaced by scan registers. Although, in the partial scan circuit, the method for generating a test pattern for use in a combinational circuit cannot be used "as is" unlike the total scan circuit, by optimally using an appropriate method for replacing a part of the test pattern with a scan operation, the test may be made easier with a minimum increase in a circuit size. However, even this method cannot completely solve the above problems (1) and (2).
When a test is performed for a total scan circuit or a partial scan circuit, it is necessary to perform all scan-ins and scan-outs for all patterns. Since a circuit has its memory elements scattered around the entire circuit and the wiring length is large, the scan clock speed for a scan-in and a scan-out is relatively slow at several megahertz [MHz]. On the other hand, the part in the circuit operating for the intended purpose operates at a clock speed of several tens of megahertz [MHz]. Therefore, it can be said that the duration required for a scan-in/scan-out determines the test period.
Assume now that the characteristic values of a scan circuit are defined as follows.
One [1] cycle of a scan clock: T.sub.scan (500 ns)
One [1] cycle of a system clock: T.sub.sys (20 ns)
The number of scan registers: N.sub.scan (2000)
The number of patterns: N.sub.pat (10000)
The following formula represents a test period T for the above signs. EQU T=N.sub.pat (T.sub.sys +2N.sub.scan T.sub.scan)
Assuming the above values in parentheses, T must be approximately twenty second [20s], which is unacceptable for inspections of chips produced in large quantities. More than 99% of the test period T is required for scan-ins and scan-outs.
As described above, the prior art has a problem in that the test period is overly prolonged.